Tue	Wed	Thu	Fri
Registration Day	NO CLASS	L1 Sep 10 Course overiew & mechanics. Basics of information.	R1 Sep 11
L2 Sep 15 Digital abstraction, combinational logic, voltage-based encoding.	R2 Sep 16	L3 Sep 17 CMOS technology; gate design; timing	R3 Sep 18
L4 Sep 22 Canonical forms; synthesis, simplification	R4 Sep 23	L5 Sep 24 Sequential logic. Lab 1 (CMOS) due	R5 Sep 25 QUIZ 1
L6 Sep 29 Storage elements, finite state machines.	R6 Sep 30	L7 Oct 01 Synchronization, metastability. Lab 2 (Adder) due	R7 Oct 02
L8 Oct 06 Pipelining; throughput and latency.	R8 Oct 07	L9 Oct 08 Case study: multipliers. Lab 3 (ALU) due	R9 Oct 09
No Lecture: Monday Schedule!	R10 Oct 14	L10 Oct 15 Models of computation, programmable architectures.	R11 Oct 16 QUIZ 2
L11 Oct 20 Beta instruction set architecture, compilation.	R12 Oct 21	L12 Oct 22 Machine language programming issues. Lab 4 (TM) due	R13 Oct 23
L13 Oct 27 Stacks and procedures.	R14 Oct 28	L14 Oct 29 Beta implementation. Lab 5 (Assy Lang) due	R15 Oct 30
L15 Nov 03 Multilevel memories; locality, performance, caches	R16 Nov 04	L16 Nov 05 Cache design issues	R17 Nov 06 QUIZ 3
L17 Nov 10 Virtual memory: mapping, protection, contexts	Veteran's Day	L18 Nov 12 Virtual machines: timesharing, OS kernels, supervisor calls Lab 6 (Beta) due	R18 Nov 13
L19 Nov 17 Devices and interrupt handlers, preemptive interrupts, real-time issues	R19 Nov 18	L20 Nov 19 Communication issues: busses, networks, protocols Lab 7 (Trap Handler) due	R20 Nov 20 QUIZ 4
L21 Nov 24 Communicating processes: semaphores, synchronization, atomicity, deadlock	R21 Nov 25	Thanksgiving
L22 Dec 01 Pipelined Beta implementation, bypassing	R22 Dec 02	L23 Dec 03 Pipeline issues: delay slots, annulment, exceptions Lab 8 (Tiny OS) due	R23 Dec 04 QUIZ 5
L24 Dec 08 Parallel processing, shared memory, cache coherence, consistency criteria	No recitation	L25 Dec 10 Wrapup Lecture! PROJECT due
Finals Week - 6.004 is over!