Tue	Wed	Thu	Fri
Registration Day	No class today!	L01 Sep 04 Course overview & mechanics. Basics of information.	R01 Sep 05
L02 Sep 09 Digital abstraction, combinational logic, voltage-based encoding	R02 Sep 10	L03 Sep 11 CMOS technology; gate design; timing	R03 Sep 12
L04 Sep 16 Canonoical forms; synthesis, simplification	R04 Sep 17	L05 Sep 18 Sequential logic. Lab #1 (CMOS) due	R05 Sep 19
L06 Sep 23 Storage elements, finite state machines.	R06 Sep 24	L07 Sep 25 Synchronization, metastability. Lab #2 (Adder) due	R07 Sep 26 Quiz #1
L08 Sep 30 Pipelining; throughput and latency.	R08 Oct 01	L09 Oct 02 Case study: multipliers. Lab #3 (ALU) due	R09 Oct 03
L10 Oct 07 Models of computation, programmable architectures.	R10 Oct 08	L11 Oct 09 Beta instruction set architecture, compilation.	R11 Oct 10 Quiz #2
Columbus Day	R12 Oct 15	L12 Oct 16 Machine language programming issues. Lab #4 (TM) due	R13 Oct 17
L13 Oct 21 Stacks and procedures.	R14 Oct 22	L14 Oct 23 Non-pipelined Beta implementation. Lab #5 (Assy Lang) due	R15 Oct 24
L15 Oct 28 Multilevel memories; locality, performance, caches	R16 Oct 29	L16 Oct 31 Cache design issues	R17 Oct 31 Quiz #3
L17 Nov 04 Virtual memory: mapping, protection, contexts	R18 Nov 05	L18 Nov 06 Virtual machines: timesharing, OS kernels, supervisor calls	R19 Nov 07
L19 Nov 11 Devices and interrupt handlers, preemptive interrupts, real-time issues	R20 Nov 12	L20 Nov 13 Communication issues: busses, networks, protocols Lab #6 (Beta) due	R21 Nov 14 Quiz #4
L21 Nov 18 Communicating processes: semaphores, synchronization, atomicity, deadlock	R22 Nov 19	L22 Nov 20 Pipelined Beta implementation, bypassing	R23 Nov 21
L23 Nov 25 Pipeline issues: delay slots, annulment, exceptions Lab #8 (Tiny OS) due	Nov 19 No recitation Lab #7 (Trap Handler) due	Thanksgiving
L24 Dec 02 Parallel processing, shared memory, cache coherence, consistency criteria	R24 Dec 03	L25 Dec 04 Wrapup Lecture!	R25 Dec 05 Quiz #5
L26 Dec 09 NO LECTURE: Design Project	R26 Dec 10 NO CLASS: Design Project Optional Project due